Damascene processing is a method for forming metal lines on integrated circuits. It involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer (inter metal dielectric). Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as copper that cannot be readily patterned by plasma etching.
In a typical Damascene process flow, metal (such as copper) is deposited onto a patterned dielectric to fill the vias and trenches formed in the dielectric layer. The resulting metallization layer is typically formed either directly on a layer carrying active devices or on another metallization layer. A stack of several metallization layers can be formed using Damascene processing. The metal-filled lines of this stack serve as conducting paths of an integrated circuit.
Before the metal is deposited into the vias and trenches of the patterned dielectric, the dielectric layer is lined with a thin layer of diffusion barrier material (e.g., Ta, TaNx, or Ta/TaNx bi-layer), and, subsequently, with a thin layer of seed layer material (e.g., Cu or Al). The diffusion barrier layer protects inter-metal dielectric (IMD) and active devices from diffusion of copper and other readily diffusing metals into these regions. The seed layer facilitates deposition of metal into the vias and trenches. For example, when electrofill methods are used for copper deposition, a copper seed layer is pre-deposited over the surface of the wafer. The copper seed layer serves as a cathode to which electrical contact is made during copper electrofill operation.
Continuous and conformal seed layers that follow the profile of the recessed features on the wafer without forming excessively thin or thick regions are highly desired. As the dimensions of the recessed features are decreasing, deposition of conformal seed layers becomes more challenging. Typically, seed layer material is deposited by physical vapor deposition (PVD) methods. In these methods neutral and/or ionized metal is sputtered from the metal target onto the wafer substrate. The neutral metal flux arrives at the wafer from all directions, and due to its non-directional nature a large portion of neutral metal flux is deposited at feature openings, often leading to formation of overhangs. The ionized metal flux is deposited more selectively on horizontal surfaces of the wafer (e.g., in the field region and in the feature bottoms) due to its greater directionality. The wafer substrate is often negatively self-biased (or may be externally biased) causing the positive metal ions to arrive at the wafer surface close to a 90° angle and to deposit predominantly on horizontal surfaces. While good coverage on horizontal surfaces can be obtained with the use of ionized metal flux, continuous conformal sidewall coverage is difficult to obtain by sputter deposition methods. Inadequate sidewall coverage, particularly in high aspect ratio features, is often observed with conventional PVD methods.
One technique which can improve sidewall coverage is resputter, also known as sputter etch. During resputter, energetic ions impinge on the exposed material on a substrate with sufficient momentum to remove the material from the substrate. The resputtered material may be permanently removed from the wafer (etched) or may be redistributed within the recessed feature. For example, seed layer material may be etched from the feature bottom and may be redeposited onto the feature sidewall. Resputtering can be performed in a plasma PVD chamber by adjusting the energy of the ions impinging on a wafer. Resputtering involves net removal of material from at least one region on the substrate, e.g., from the bottom of a recessed feature. Resputtering can be used to remove seed layer material from excessively thick regions and to improve coverage in excessively thin regions.
While resputtering is an attractive method for achieving conformal seed layer coverage, it is noted that aggressive seed layer sputter etching may involve exposing diffusion barrier material which underlies the seed layer, and, can inadvertently remove it. Such removal of diffusion barrier material is undesirable and should be, if possible, avoided. Removal of diffusion barrier layer can lead to excessively thin diffusion barrier layers, or, in the worst case, dielectric may be exposed and may be contaminated with conductive seed layer material. Therefore, methods for selective sputter etching of seed layer material in the presence of diffusion barrier material are needed.
Several methods for selective resputtering were described in US Patent application publication No. 2006/0030151 by Ding at al., published on Feb. 9, 2006. These methods are based on performing resputtering with light (low atomic weight) inert gas ions, particularly with helium ions. Helium inert gas is introduced into the PVD process chamber and is ionized in a plasma. When light inert gas ions strike the substrate surface, they are capable of selectively sputter etching copper seed layer in the presence of exposed tantalum diffusion barrier. Therefore, with light ion resputtering, seed layer material is removed or redistributed without significantly removing the diffusion barrier material.
Light ion resputtering, however, has several disadvantages, which include high cost of light inert gases (e.g., He), the necessity of PVD apparatus modification to accommodate delivery of light inert gases into the process chamber, and, the necessity of a particular apparatus configuration which allows generation of light inert gas ions without generating substantial amounts of heavier metal ions.
New methods for selective resputtering of seed layers are needed.